1. Field
Example embodiments disclosed herein relate to a semiconductor device and a method of forming the same. Other example embodiments relate to a nonvolatile memory device having a floating gate and a method of forming the same.
2. Description of the Related Art
Memory devices are classified into volatile memory devices and non-volatile memory devices depending on whether or not a power supply is required so as to maintain stored information. Volatile memory devices (e.g., DRAMs and/or SRAMs) may have a relatively rapid operation speed, but power must be continuously supplied so as to maintain stored information. On the contrary, because non-volatile memory devices (e.g., flash memories) may not have such a limitation, they may be being widely used in portable electronic appliances of which demands have sharply increased.
Due to higher integration of semiconductor devices, there may be various technical difficulties in manufacturing non-volatile memory devices. The enhancement of integration may be followed by a decrease in spacing between adjacent word lines, which may make it relatively difficult to improve structures and characteristics of the non-volatile memory devices.
FIG. 1 is a diagram of a cell array of a non-volatile memory device according to the conventional art. Referring to FIG. 1, a device isolation pattern 14 defining an active region 12 may be provided in a semiconductor substrate 10. A floating gate electrode 22 may be provided on the active region 12, and a gate insulation layer 21 may be interposed or inserted between the floating gate electrode 22 and the active region 12. A control gate electrode 24 may be provided over the floating gate electrode 22, crossing the active region 12 and the device isolation pattern 14. The control gate electrode 24 may be used as a word line for selecting a specific cell in a cell array comprised of a plurality of memory cells. An intergate dielectric layer 23 may be interposed or inserted between the control gate electrode and the floating gate electrode 22.
For more rapid and more effective operation of this kind of non-volatile memory device, it may be required that the control gate electrode and the floating gate electrode have a sufficiently large coupling ratio, but the decrease in spacing between the word lines may make it relatively difficult to secure the sufficiently large coupling ratio. The coupling ratio may represent efficiency of a voltage applied to the control gate electrode that may be transferred to the floating gate electrode, and it may depend on a dielectric constant of an insulating layer interposed or inserted therebetween and a coupling area therebetween. To increase the coupling ratio, it may be required to decrease spacing between these electrodes or to increase the dielectric constant of the intergate dielectric layer, but such approaches may have technical limitations. One method to increase the coupling ratio on the present technical level may be to increase the coupling area between those electrodes.
However, according to the conventional art, the increase of the coupling area may cause an increase in electrical interference between the adjacent floating gate electrodes. The reason for the electrical interference may be a parasitic capacitor ‘Cfgx’ between a floating gate electrode (positioned at the center in FIG. 1) and an adjacent floating gate electrode in the same word line, a parasitic capacitor ‘Cfgy’ between floating gate electrodes of adjacent word lines, a parasitic capacitor ‘Cfgcg’ between the floating gate electrode and control gate electrodes of adjacent word lines.
FIG. 3A illustrates a floating gate electrode according to the conventional art, of which section taken along a word line direction may have a rectangle structure or an inverse T structure. In FIG. 3A, while the floating gate electrode having the inverse T shape may have a smaller sectional area compared with the general rectangle structure, it may be understood that a coupling area between the floating gate electrode and the overlying control gate electrode may increase. In the inverse T shaped floating gate structure, the sectional area may be l1h1+l2h2 and the coupling area with the control gate electrode may be proportional to 2(h1+h2)+l1.
If the aforementioned electrical interferences are repeated, information stored in a cell may be changed. Considering these facts, the floating gate electrode 22 may have a structure capable of increasing the coupling area between the floating gate electrode 22 and the control gate electrode 24 without increasing a facing area between the floating gate electrode and the control gate electrodes of adjacent word lines and a facing area between the floating gate electrodes of adjacent word lines. However, it may be difficult to do so with the cell structure of the non-volatile memory device according to the conventional art.